期刊文章: 

[1] Fu, Rongliang, Junying Huang, Haibin Wu, Xiaochun Ye, Dongrui Fan, and Tsung-Yi Ho. "JBNN: A Hardware Design for Binarized Neural Networks Using Single-Flux-Quantum Circuits." IEEE Transactions on Computers 71, no. 12 (2022): 3203-3214. 

[2] Huang, Junying, Rongliang Fu, Xiaochun Ye, and Dongrui Fan. "A survey on superconducting computing technology: circuits, architectures and design tools." CCF Transactions on High Performance Computing 4, no. 1 (2022): 1-22. 

[3] Fu, Rong-Liang, Guang-Ming Tang, Junying Huang, and Zhi-Min Zhang. "An Automatic placement algorithm for superconducting rapid single-flux-quantum logic circuits." IEEE Transactions on Applied Superconductivity 31, no. 5 (2021): 1-5. 

会议文章： 

[1] Rongliang Fu, Junying Huang, Mengmeng Wang, Yoshikawa Nobuyuki, Bei Yu, Tsung-Yi Ho, Olivia Chen. "BOMIG: A Majority Logic Synthesis Framework for AQFP Logic." Design, Automation and Test in Europe (DATE) 2023 (accepted). 

[2] Fu, Rongliang, Junying Huang, and Zhi-Min Zhang. "Equivalence Checking for Superconducting RSFQ Logic Circuits." In Proceedings of the 2021 on Great Lakes Symposium on VLSI, pp. 51-56. 2021. 

[3] Fu, Rongliang, Zhi-Min Zhang, Guang-Ming Tang, Junying Huang, Xiao-Chun Ye, Dong-Rui Fan, and Ning-Hui Sun. "Design Automation Methodology from RTL to Gate-level Netlist and Schematic for RSFQ Logic Circuits." In Proceedings of the 2020 on Great Lakes Symposium on VLSI, pp. 145-150. 2020. 

[4] Huang, Junying, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, and Zhimin Zhang. "Instruction Vulnerability Test and Code Optimization Against DVFS Attack." In 2019 IEEE International Test Conference in Asia (ITC-Asia), pp. 49-54. IEEE, 2019. 

[5] Zhang, Kuozhong, Junying Huang, Jing Ye, Xiaochun Ye, Da Wang, Dongrui Fan, Huawei Li, Xiaowei Li, and Zhimin Zhang. "iATPG: Instruction-level Automatic Test Program Generation for Vulnerabilities under DVFS attack." In 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 287-292. IEEE, 2019. 

专利： 

[1]黄俊英;付荣亮;张志敏，一种超导二值神经网络加速方法及加速器，申请号：CN202210513312.7. 

[2]黄俊英;付荣亮;张阔中;叶笑春;张志敏;范东睿，生成面向超导RSFQ电路的多扇出时钟信号的方法，申请号：CN202110446390.5 

[3]黄俊英;张阔中;叶笑春;张志敏;范东睿，用于双时钟架构的超导RSFQ电路布局方法，申请号：CN202110442343.3 

[4]黄俊英;付荣亮;张阔中;叶笑春;张志敏;范东睿，生成面向超导RSFQ电路的 

多扇出时钟信号的方法，申请号：CN202010703091.0 

[5]张阔中;黄俊英;张志敏;唐光明，基于超导异或门生成时钟信号的方法以及时钟发生器，申请号：CN202210048631.5 

[6]张阔中;黄俊英;张志敏;唐光明，超导译码器装置，申请号： CN202110689803.2 

[7]王中旗;黄俊英;张志敏;叶笑春;范东睿，跨平台光纤传输系统，申请号： CN202210764423.5 

[8]王中旗;黄俊英;张志敏;叶笑春;范东睿，板间通信接口系统，申请号： CN202210764461.0 

[9]王中旗;黄俊英;张志敏;叶笑春;范东睿，光纤通信转接系统，申请号： CN202210764499.8 

[10]付荣亮;黄俊英;张阔中;唐光明;叶笑春;范东睿;张志敏，一种生成面向超导RSFQ电路的多扇出信号的方法，申请号： CN202010709748.4 

[11]张阔中;黄俊英;张志敏;唐光明，超导寄存器堆装置及其控制方法，申请号： CN202110439614.X 

[12]王中旗;张志轩;黄俊英;张志敏;叶笑春;范东睿，针对低温多芯片计算系统的模拟方法及其系统，申请号： CN202210880357.8 

[13]张阔中;张志敏;唐光明;黄俊英，超导脉冲计数器，申请号： CN202210598684.4 

[14]张志敏;唐光明;张阔中;黄俊英;付荣亮;叶笑春;范东睿，一种超导流水线电路及处理器，申请号： CN202010875646.X 

[15]张志敏;唐光明;张阔中;黄俊英;付荣亮;叶笑春;范东睿，一种超导并行寄存器堆装置，申请号： CN202010876462.5 

[16]张阔中;张志敏;唐光明;黄俊英;付荣亮;叶笑春;范东睿，超导处理器及其输入输出控制模块，申请号： CN202110266205.4