2013年9月 - 今，中国科学院计算技术研究所，副研究员

2009年7月 - 2013年9月，中国科学院计算技术研究所，助理研究员

2013年1月 - 2013年8月，瑞士洛桑联邦理工大学（EPFL），访问学者

2004年9月 - 2009年7月，中国科学院计算技术研究所，计算机系统结构，工学博士

1999年9月 - 2004年7月，中国科学技术大学，电子科学与技术，理学学士

期刊文章:

[1] Da Wang, Yu Hu, Huawei Li, and Xiaowei Li, “The Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor”, Journal of Computer Science and Technology (JCST), 2008, 23(6): 1037-1046. 

[2] Dongrui Fan, Hao Zhang, Da Wang, Xiaochun Ye, Fenglong Song, Guojie Li, Ninghui Sun, “High-Efficient Architecture of Godson-T Many-Core Processor,” IEEE Micro, March/ April 2012, pp. 38-47.(通讯作者)

[3] Weizhi Xu, Hui Yu, Dianjie Lu, Fenglong Song, Da Wang, Xiaochun Ye, Songwei Pei, Dongrui Fan, Hongtao Xie, Fast and scalable lock methods for video coding on many-core architecture, Journal of Visual Communication and Image Representation, Volume 25, Issue 7, October 2014, Pages 1758-1762, ISSN 1047-3203. 

[4] Fei Wang, Da Wang, Haigang Yang, Xianghui Xie, Dongrui Fan, “On-Chip Generating FPGA Test Configuration Bitstreams to Reduce Manufacturing Test Time”, Chinese Journal of Electronics, 2016, 25(1):64-70. 通讯作者

[5] Xiaowei Shen, Xiaochun Ye, Xu Tan, Da Wang, Lunkai Zhang, Wenming Li, Zhimin Zhang, Dongrui Fan, Ninghui Sun. An Efficient Network-on-Chip Router for Dataflow Architecture. Journal of Computer Science and Technology (JCST), 32(1):1-15 Jan. 2017. 

[6] Xu Tan, Xiaochun Ye, Xiaowei Shen, Yuanchao Xu, Da Wang, Lunkai Zhang, Wenming Li, Dongrui Fan, Zhimin Tang. A Pipelining Loop Optimization Method for Dataflow Architecture. Journal of Computer Science and Technology (JCST), 33(1):116-130, Jan. 2018.  

[7] Xu Tan, Xiaowei Shen, Xiaochun Ye, Da Wang, Dongrui Fan, Lunkai Zhang, Wenming Li, Zhimin Zhang, Zhimin Tang. A Non-Stop Double Buffering Mechanism for Dataflow Architecture. Journal of Computer Science and Technology (JCST), 33(1):145-157, Jan. 2018.  

[8] Wenming Li, Xiaochun Ye, Da Wang, Hao Zhang, Zhimin Tang, Dongrui Fan, Ninghui Sun. PIM-WEAVER: A High Energy-efficient, General-purpose Acceleration Architecture for String Operations in Big Data Processing. Sustainable Computing: Informatics and Systems. 21(3): 2019. pp129142.

[9] Xiaochun Ye, Xu Tan, Meng Wu, Yujing Feng, Da Wang, Hao Zhang, Songwen Pei, Dongrui Fan. An Efficient Dataflow Accelerator for Scientific Applications. Future Generation Computer Systems (FGCS), 112(2020) :580-588. 

[10] Yi Li, Meng Wu, Xiaochun Ye, Wenming Li, Rui Xue, Da Wang, Hao Zhang, Dongrui Fan. An efficient scheduling algorithm for dataflow architecture using loop-pipelining. Information Sciences. 547 (2021): 1136–1153. 

[11] Yujing Feng, Dejian Li, Xu Tan, Xiaochun Ye, Dongrui Fan, Wenming Li, Da Wang, Hao Zhang, Zhimin Tang. Accelerating data transfer in dataflow architectures through a look-ahead acknowledgment mechanism. Journal of Computer Science and Technology (JCST), 2022.  

[12] Yaoyao Yan, Da Wang, Jing Ye, Hui Yu, Dianjie Lu, Yuang Zhang, Weizhi Xu, Fang’ai Liu, DCHF_T: A multi-dimensional adaptive compression approach for transformer-based models. Neurocomputing 656 (2025) 131071. 

[13] Yaoyao Yan, Hui Yu, Da Wang, Jing Ye, Fang’ai Liu, Weizhi Xu, STP: Special token prompt for parameter-efficient tuning of pre-trained language models, Expert Systems With Applications 284 (2025) 127665. 

会议文章：

[1] Da Wang, Xiaoxin Fan, Xiang Fu, Hui Liu, Ke Wen, Rui Li, Huawei Li, Yu Hu, and Xiaowei Li, “The Design-for-Testability Features of A General Purpose Microprocessor”, In Proc. of IEEE Intl. Test Conf. (ITC), 2007, Session 9.2.  

[2] Dongrui Fan, Hao Zhang, Da Wang, Xiaochun Ye, Fenglong Song, Junchao Zhang, and Lingjun Fan. High-Efficient Architecture of Godson-T Many-Core Processor. In the proceeding of the 23rd HotChips Conference, Aug. 17-19, 2011, Stanford Uniersity, CA. 通讯作者

[3] Dongrui Fan, Wenming Li, Xiaochun Ye, Da Wang, Hao Zhang, Zhimin Tang, Ninghui Sun. SmarCo: An Efficient Many-Core Processor for High-Throughput Applications in Datacenters. In the 24th IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2018.

专利：

[1] 王达、胡瑜、李华伟、李晓维， 一种内嵌式三维容错存储器结构电路及其容错方法。ZL200710176138.7.

[2] 谢远江，王达，胡瑜，李晓维，存储器内建自修复系统及自修复方法。ZL200810117443.3.

[3] 徐卫志、焦帅、张浩、刘志勇、范东睿、雷峥蒙、宋风龙、王达，众核处理器片上同步方法和其系统，ZL201010221087.7.

[4] 叶寒栋、曹炯、叶笑春、王达，并行模拟多个处理器的方法及系统、调度器，ZL201110269208.X.

[5] 叶寒栋、曹炯、叶笑春、王达，并行模拟多个处理器的方法及系统、调度器，ZL201110252377.2.

[6] 范灵俊、唐士斌、王达、张浩、范东睿，用于处理器的动态组相联高速缓存装置及其访问方法，ZL201210134204.5. 

[7] 唐士斌、宋风龙、王达、范东睿，程序的线程关系确定方法、设备及系统，ZL201210382173.5.

[8] 张帅、宋风龙、王达、张浩，多机系统、用于优化多机系统功耗的方法及装置，ZL201310001368.5.

[9] 范东睿、叶笑春、王达、张浩，一种实时多任务调度方法和装置，ZL201210551909.7

[10] 范东睿、宋风龙、王达、叶笑春，内存访问处理方法、装置及系统，ZL201310339295.0

[11] 张轮凯、范东睿、叶笑春、王达，基于多内核处理器的一致性处理方法和装置，ZL201310260830.3

[12] Fan Lingjun, Tang Shibin, Wang Da, Zhang Hao, Fan DongRui, DYNAMIC SET ASSOCIATIVE CACHE APPARATUS FOR PROCESSOR AND ACCESS METHOD THEREOF, 02 May 2013, EP13784394.2. 欧盟专利

[13] Ye Handong, Cao Jiong , Ye Xiaochun, Wang Da, METHOD, SYSTEM, AND SCHEDULER FOR SIMULATING MULTIPLE PROCESSORS IN PARALLEL, 13 Aug 2012, 83181120US03. 美国专利

[14] Ye Handong, Cao Jiong , Ye Xiaochun, Wang Da, METHOD AND SYSTEM FOR SIMULATING MULTIPLE PROCESSORS IN PARALLEL AND SCHEDULER, 13 Sep 2012, 83181123US04. 美国专利

[15] Ye Handong, Cao Jiong , Ye Xiaochun, Wang Da, METHOD, SYSTEM, AND SCHEDULER FOR SIMULATING MULTIPLE PROCESSORS IN PARALLEL, 27 Aug 2012, EP12828153.2, 83181120EP04

[16] Ye Handong, Cao Jiong , Ye Xiaochun, Wang Da, METHOD AND SYSTEM FOR SIMULATING MULTIPLE PROCESSORS IN PARALLEL AND SCHEDULER, 13 Sep 2012, EP12832221.1, 83181123EP03

[17] 李文明，叶笑春，孙凝晖，范东睿，王达，马丽娜，朱亚涛，张洋，一种异常事件自动推送及基于历史操作的监控方法及系统，ZL 201611148500.5

[18] 贾瑞花，郭楠，王达，叶笑春，范东睿，一种智能音响及其播放控制方法，ZL 201810916504.6

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