现任处理器芯片全国重点实验室副主任，中国计算机学会（CCF）集成电路设计专委主任，中国计量测试学会集成电路测试专委副主任兼秘书长，IEEE Design & Test、IEEE TVLSI、JCST、《计算机研究与发展》等期刊编委。曾获国家技术发明二等奖、北京市科技进步一等奖、CCF技术发明一等奖、5次国际会议/国际期刊最佳论文奖等。 

工作/教育经历：

2008年10月 — 今 ：中科院计算所，研究员 

2001年10月 — 2008年9月 ：中科院计算所，副研究员 

2001年7月 — 2001年9月：中科院计算所，助理研究员 

2009年8月 — 2010年8月：美国UCSB大学，访问学者 

1996年9月— 2001年7月：中科院计算所，硕士生/博士生

李华伟，郑武东，温晓青，赖李洋，叶靖，李晓维。数字集成电路测试：理论、方法与实践。清华大学出版社，ISBN-978-7-302-66203-7，2024年6月。

期刊论文：

[1] Ying Zhang, Aodi He, Jiaying Li, Ahmed Rezine, Zebo Peng, Erik Larsson, Tao Yang, Jianhui Jiang, Huawei Li, "On Modeling and Detecting Trojans in Instruction Sets," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.43, No.10, pp.3226-3239, 2024.

[2] Yintao He, Bin Li, Ying Wang, Cheng Liu, Huawei Li and Xiaowei Li, "A Task-Adaptive In-Situ ReRAM Computing for Graph Convolutional Networks," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.43, No.9, pp.2635-2646, 2024.

[3] Xiaoze Lin, Liyang Lai and Huawei Li, "Parallel Static Learning Toward Heterogeneous Computing Architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.43, No.3, pp.983-993, 2024.

[4] Wen Li, Ying Wang, Cheng Liu, Yintao He, Lian Liu, Huawei Li, Xiaowei Li, “On-line Fault Protection for ReRAM-based Neural Networks,” IEEE Transactions on Computers (TC),Vol.72, No.2, pp.423-437, 2023.

[5] Kaiwei Zou, Ying Wang, Long Cheng, Huawei Li, Xiaowei Li, “CAP: Communication-aware Automated Parallelization for Deep Learning Inference on CMP Architectures,” IEEE Transactions on Computers (TC), Vol.71, No.7, pp. 1626 - 1639, 2022.

[6] Yintao He, Ying Wang, Huawei Li, Xiaowei Li, "Saving Energy of RRAM-based Neural Accelerator through State-Aware Computing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.41, No.7, pp. 2115 - 2127, 2022.

[7] Ying Wang, Yintao He, Long Cheng, Huawei Li, Xiaowei Li, "A Fast Precision Tuning Solution for Always-On DNN Accelerators,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.41, No.5, pp.1236-1248, 2022.

[8] Shengwen Liang, Ying Wang, Cheng Liu, Lei He, Huawei Li, Dawen Xu, Xiaowei Li, “EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks,” IEEE Transactions on Computers (TC), Vol.70, No.9 pp. 1511-1525, 2021. (BEST PAPER AWARD)

[9] Ying Wang, Yongchen Wang, Cong Shi, Long Cheng, Huawei Li, Xiaowei Li, “An Edge 3D CNN Accelerator for Low Power Activity Recognition,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.40, No.5, pp.918-930, 2021.

[10] Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li, “A Guaranteed Secure Scan Design based on Test Data Obfuscation by Cryptographic Hash,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.39, No.12, pp.4524-4536, Dec. 2020.

[11] Liyang Lai, Hans Tsai, Huawei Li, “GPGPU-based ATPG System: Myth or Reality?” IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol.39, No.1, pp.239-247, 2020.

[12] Ying Wang, Huawei Li, Long Cheng, Xiaowei Li, "A QoS-QoR Aware CNN Accelerator Design Approach,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.38, No.11, pp. 1995-2007, 2019. 

[13] Yun Cheng, Huawei Li, Ying Wang, Xiaowei Li, “Cluster Restoration-Based Trace Signal Selection for Post-Silicon Debug,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol.38, No.4, pp.767-779, 2019. 

[14] Ying Wang, Huawei Li, Xiaowei Li, “A Case of On-chip Memory Sub-system Design for Low-Power CNN Accelerators,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol.37, No.10, pp.1971-1984, 2018. 

[15] Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li, “On Trace Buffer Reuse based Trigger generation in Post Silicon Debug,” IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol.37, No.10, pp.2166-2179, 2018. 

[16] Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li, “A Low Overhead In-Network Data Compressor for the Memory Hierarchy of Chip Multi-Processors,” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol.37, No.6, pp.1265-1277, 2018. 

[17] Haihua Shen, Hua-Zhe Tan, Huawei Li, Feng Zhang, Xiaowei Li, “LMDet: A “Naturalness” Statistical Method for Hardware Trojan Detection,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.26, No.4, pp.720-732, 2018. 

[18] Ying Wang, Jiachao Deng, Yuntan Fang, Huawei Li, and Xiaowei Li, “Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 25, No. 10, pp.2736-2748, 2017. 

[19] Ying Wang, Yinhe Han, Cheng Wang, Huawei Li, Xiaowei Li, “Retention-Aware DRAM Assembly and Repair for Future FGR Memories”, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 36, No.5, pp.705-718, 2017. 

[20] Jian Wang, Huawei Li, Tao Lv, Tiancheng Wang, Xiaowei Li, and Sandip Kundu, “Abstraction-Guided Simulation Using Markov Analysis for Functional Verification,” IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No.2, pp.285-297, 2016. 

[21] Yanhong Zhou, Tiancheng Wang, Huawei Li, Tao Lv, Xiaowei Li, “Functional Test Generation for Hard-to-reach States Using Path Constraint Solving,” IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems (TCAD), Vol. 35, No.6, pp.999-1011, 2016. 

[22] Guihai Yan, Faqiang Sun, Huawei Li, Xiaowei Li, “CoreRank: Redeeming Imperfect Silicon by Dynamically Quantifying Core-level Healthy Condition of Manycore Processors,” IEEE Transactions on Computers (TC), Vol. 65, No.3, pp.716-729, 2016. 

[23] Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li, “PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3D Die-Stacked PCM”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol.24, No.5, pp.1613-1625, 2016. 

[24] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Data Remapping for Static NUCA in Degradable Chip Multiprocessors”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.5, pp. 879-892, 2015. 

[25] Ying Wang, Lei Zhang, Yinhe Han, Huawei Li, Xiaowei Li, “Economizing TSV resources in 3D Network-on-Chip design”, IEEE Transactions on Very Large Scaled Integration Systems (TVLSI), Vol. 23, No.3, pp. 493-506, 2015. 

[26] Dawen Xu, Huawei Li, Amirali Ghofrani, K.-T. Cheng, Yinhe Han, Xiaowei Li, “Test-Quality Optimization for Variable n-Detections of Transition Faults,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.8, pp. 1738-1749, August 2014. 

[27] Binzhang Fu, Yinhe Han, Huawei Li, Xiaowei Li, “ZoneDefense: A Fault-Tolerant Routing for 2D Meshes Without Virtual Channels,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.1, pp.113-126, 2014. 

[28] Yuntan Fang, Huawei Li, and Xiaowei Li, “Lifetime enhancement techniques for PCM-based image buffer in multimedia applications,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.22, No.6, pp. 1450-1455, June 2014. 

[29] Song Jin, Yinhe Han, Huawei Li, Xiaowei Li, “Unified Capture Scheme for Small Delay Defect Detection and Aging Prediction,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.5, May 2013, pp.821-833. 

[30] Ying Zhang, Huawei Li, Xiaowei Li, “Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1220-1233. 

[31] Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Test Path Selection for Capturing Delay Failures Under Statistical Timing Model,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.21, No.7, July 2013, pp.1210-1219. 

[32] Xiang Fu, Huawei Li, Xiaowei Li, “Testable path selection and grouping for faster than at-speed testing,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.2, 2012, pp.236-247. 

[33] Songwei Pei, Huawei Li, Xiaowei Li, “Flip-Flop Selection for Partial Enhanced Scan to Reduce Transition Test Data Volume,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.12, 2012, pp. 2157-2169. 

[34] Songwei Pei, Huawei Li, Xiaowei Li, “A High-Precision On-Chip Path Delay Measurement Architecture,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.20, No.9, 2012, pp.1565-1577. 

[35] Ying Zhang, Huawei Li, Yinghua Min, Xiaowei Li, “Selected Transition Time Adjustment for Tolerating Crosstalk Effects on Network-on-Chip Interconnects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.10, 2011, pp.1787-1800. 

[36] Minjin Zhang, Huawei Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling Effects,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.19, No.11, 2011, pp.1969-1982. 

[37] Huawei Li, and Xiaowei Li, “Selection of Crosstalk-induced Faults in Enhanced Delay Test,” Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 21, No.2, 2005, pp.181-195. 

[38] Huawei Li, Zhongcheng Li, and Yinghua Min, “Reduction of Number of Paths to be tested in Delay Testing,” Journal of Electronic Testing: Theory and Applications(JETTA), Vol.16, No.5, Oct. 2000, pp. 477-485. 

[39] 李华伟, 闵应骅, 李忠诚, “有限状态机的行为阶段聚类及其对测试的应用”, 《中国科学》E辑, Vol.32, No.6, 2002, pp.846-860.

[40] 李华伟, 李忠诚, 闵应骅, “带时间参数的测试产生”, 《计算机学报》, Vol.22, No.4, 1999, pp.390-394.

会议论文：

[1] Feng Gu, Mingjun Wang, Jianan Mu, et al., “DDP-Fsim: Efficient and Scalable Fault Simulation for Deterministic Patterns with Two-Dimensional Parallelism,” IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2024. (BEST PAPER Nomination)

[2] Kaiyan Chang, Zhirong Chen, Yunhao Zhou, et al., “Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation,” IEEE/ACM ICCAD, 2024.

[3] Wenxing Li, Hongqin Lyu, Shengwen Liang, TianchengWang and Huawei Li, “SmartATPG: Learning-based Automatic Test Pattern Generation with Graph Convolutional Network and Reinforcement Learning,” ACM/IEEE 61st Design Automation Conference (DAC), San Francisco, CA, USA,  Article A26, 2024.Article A296, 2024.

[4] Kaiyan Chang, Kun Wang, Nan Yang, et al., “Data is all you need: Finetuning LLMs for chip design via an automated design-data augmentation framework,” ACM/IEEE 61st DAC, Article A60, 2024.

[5] Jianan Mu, Husheng Han, Shangyi Shi, et al., “Alchemist: A Unified Accelerator Architecture for Cross-Scheme Fully Homomorphic Encryption,” ACM/IEEE 61st DAC, Article A26, 2024.

[6] Lian Liu, Zhaohui Xu, Yintao He, et al.,“Drift: Leveraging Distribution-based Dynamic Precision Quantization for Efficient Deep Neural Network Acceleration,” ACM/IEEE 61st DAC, Article A140, 2024.

[7] Yibo Du, Ying Wang, Bing Li, et al., “Chiplever: Towards Effortless Extension of Chiplet-based System for Fully Homomorphic Encryption,” ACM/IEEE 61st DAC, Article A243, 2024.

[8] Wenxing Li, Hongqin Lyu, Shengwen Liang, Ttiancheng Wang, Pengyu Tian and Huawei Li, "Intelligent Automatic Test Pattern Generation for Digital Circuits Based on Reinforcement Learning," IEEE 32nd Asian Test Symposium (ATS), 2023. (BEST PAPER AWARD)

[9] Cangyuan Li, Ying Wang, Huawei Li and Yinhe Han, "APPEND: Rethinking ASIP Synthesis in the Era of AI," ACM/IEEE 60th DAC, 2023.

[10] Yintao He, Songyun Qu, Ying Wang, Bing Li, Huawei Li, Xiaowei Li, "InfoX: An Energy-Efficient ReRAM Accelerator Design with Information-Lossless Low-Bit ADCs,” ACM/IEEE 59th DAC, 2022.

[11] Shengwen Liang, Ying Wang, Ziming Yuan, Cheng Liu, Huawei Li, Xiaowei Li, "VStore: In-Storage Graph Based Vector Search Accelerator,” ACM/IEEE 59th DAC, 2022.

[12] Cangyuan Li, Ying Wang, Cheng Liu, Shengwen Liang, Huawei Li, Xiaowei Li, “GLIST: Towards In-Storage Graph Learning,” Proc. USENIX Annual Technical Conference (ATC), pp.225-238, 2021.

[13] Yongchen Wang, Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li, “An Activity Analysis Architecture From Compressed Video Streams,” ACM/IEEE 58th DAC, 2021.

[14] Yintao He, Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li, “TARe: Task-Adaptive in-situ ReRAM Computing for Graph Learning,” ACM/IEEE 58th DAC, 2021.

[15] Lei He, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li, “GCiM: A Near-Data Processing Accelerator for Graph Construction,” ACM/IEEE 58th DAC, 2021.

[16] Huawei Li, Xiaowei Li, Yu Huang, Ying Wang, Gary Guo，“Special Session - Test for AI Chips: from DFT to On-line Testing,” 2021 IEEE 38th VLSI Test Symposium (VTS), San Diego, CA, USA, April 2021.

[17] Yintao He, Ying Wang, Xiandong Zhao, Huawei Li, Xiaowei Li “Towards State-Aware Computation in ReRAM Neural Networks,” ACM/IEEE 57th DAC, San Francisco, CA, USA, Article No. 73, 2020.

[18] Yongchen Wang, Ying Wang, Huawei Li, Yinhe Han, Xiaowei Li, “An Efficient Deep Learning Accelerator for Compressed Video Analysis,” ACM/IEEE 57th DAC, Article No. 167, 2020.

[19] Shengwen Liang, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li, “DeepBurning-GL: an Automated Framework for Generating Graph Neural Network Accelerators,” IEEE 39th ICCAD, 2020.

[20] Wen Li, Ying Wang, Huawei Li, Xiaowei Li “RRAMedy: Protecting ReRAM-based Neural Network from Permanent and Soft Faults During Its Lifetime,” IEEE 37th International Conference On Computer Design (ICCD), 2019. (BEST PAPER AWARD) 

[21] Yintao He, Ying Wang, Huawei Li, Xiaowei Li “An Agile Precision-Tunable CNN Accelerator based on ReRAM,” IEEE/ACM 38th ICCAD, 2019. 

[22] Shengwen Liang, Ying Wang, Youyou Lu, Zhe Yang, Huawei Li, Xiaowei Li. “Cognitive SSD: A Deep Learning Engine for In-Storage Data Retrieval,” USENIX ATC, Renton, USA, pp.395-410, 2019. 

[23] Yongchen Wang, Ying Wang, Huawei Li, Shi Cong, Xiaowei Li, “Systolic Cube: A Spatial 3D CNN Accelerator Architecture for Low Power Activity Recognition”, IEEE/ACM 56th DAC, Article No. 210, 2019. 

[24] Ying Wang, Shenwen Liang, Huawei Li, Xiaowei Li, “A None-Sparse Inference Accelerator that Distills and Reuses the Computation Redundancy in CNNs”, IEEE/ACM 56th DAC, Article No. 202, 2019. 

[25] Ying Wang, Wen Li, Huawei Li, Xiaowei Li, “Lightweight Timing Channel Protection for Shared DRAM Controller,” IEEE 49th International Test Conference (ITC), 2018. 

[26] Ying Wang, Wen Li, Huawei Li, Xiaowei Li, “Leveraging DRAM Refresh to Protect the Memory Timing Channel of Cloud Chip Multi-Processors,” IEEE 2nd International Test Conference in Asia (ITC-Asia), pp.73-78, 2018. (BEST PAPER AWARD)

[27] Ying Wang, Huawei Li, Xiaowei Li, “Real-Time meets Approximate Computing: An Elastic Deep Learning Accelerator Design with Adaptive Trade-off between QoS and QoR,” IEEE/ACM 54th DAC, Article No. 33, 2017. 

[28] Ying Zhang, Krishnendu Chakrabarty, Huawei Li, Jianhui Jiang, “Software-based Online Self-Testing of Network-on-Chip using Bounded Model Checking,” IEEE 48th ITC, Paper 11.1, 2017. 

[29] Huawei Li, Xiaowei Li, “Formal Verification Practices in Industry,” IEEE 35th VTS, Paper 10C, 2017. 

[30] Yun Cheng, Huawei Li, Ying Wang, Yingke Gao, Bo Liu, Xiaowei Li, “Flip-flop Clustering based Trace Signal Selection for Post-Silicon Debug,” IEEE 35th VTS, Paper 3A-2, 2017. 

[31] Ying Wang, Huawei Li, Xiaowei Li, “Re-architecting the On-chip memory Sub-system of Machine-Learning Accelerator for Embedded Devices,” IEEE 35th ICCAD, 2016. 

[32] Ying Wang, Jie Xu, Yinhe Han, Huawei Li, Xiaowei Li, “DeepBurning: Automatic Generation of FPGA-based Learning Accelerators for the Neural Network Family,” IEEE/ACM 53rd DAC, 2016. 

[33] Ying Wang, Yinhe Han, Jun Zhou, Huawei Li, Xiaowei Li, “DISCO: A Low Overhead In-Network Data Compressor for Energy-Efficient Chip Multi-Processors,” IEEE/ACM 53rd DAC, 2016. 

[34] Huina Chao, Huawei Li, Tiancheng Wang, Xiaowei Li and Bo Liu, “An accurate algorithm for computing mutation coverage in model checking,” IEEE 47th ITC, Paper 16.2, 2016. 

[35] Yanhong Zhou, Huawei Li, Tiancheng Wang, Bo Liu, Yingke Gao, Xiaowei Li, “Path Constraint Solving based Test Generation for Observability-enhanced Branch Coverage,”, IEEE 34th VTS, Paper 1B-2, 2016. 

[36] Yuntan Fang, Huawei Li, Xiaowei Li, “RSAK: Random Stream AttacK for Phase Change Memory in Video Applications,” IEEE 31st VTS, Paper 10B-3, 2013. 

[37] Songwei Pei, Huawei Li, and Xiaowei Li, “A Unified Test Architecture for on-Line and Off-Line Delay Fault Detections", IEEE 29th VTS, pp.272-277, 2011. 

[38] Binzhang Fu, Yinhe Han, Jun Ma, Huawei Li, and Xiaowei Li, “An Abacus Turn Model for Time/Space-Efficient Reconfigurable Routing,” International Symposium on Computer Architecture (ISCA), pp.259-270, 2011.

[39] Huawei Li, Dawen Xu, K.-T. Cheng, “GPU-accelerated fault simulation and its new applications,” IEEE International Symposium on VLSI Design, Automation and Test, Taiwan, 2011. (Invited Talk)

[40] Huawei Li, Dawen Xu, Yinhe Han, K.-T. Cheng, Xiaowei Li, “nGFSIM: A GPU-Based 1-to-n-Detection Fault Simulator and its Applications,” IEEE 41st ITC, Paper 12.1, 2010. 

[41] Zijian He, Tao Lv, Huawei Li, Xiaowei Li, “Fast path selection for testing of small delay defects considering path correlations,” IEEE 28th VTS, pp.3-8, 2010. 

[42] Huawei Li, Peifu Shen, and Xiaowei Li, “Robust Test Generation for Crosstalk-Induced Path Delay Faults,” IEEE 24th VTS, Berkeley, CA, USA, 2006. 

[43] Huawei Li, Yue Zhang, and Xiaowei Li, “Delay Test Pattern Generation Considering Crosstalk-induced Effects,” IEEE 12th Asian Test Symposium (ATS), pp.178-183, 2003.

专用处理器芯片自动设计技术与应用：2021年度中国计算机学会技术发明一等奖。

北斗三号综合电子计算机系统关键技术及应用：2020年度北京市科学技术奖技术进步一等奖。

微处理器全生命周期可靠设计关键技术及应用：2018年度中国电子学会科学技术奖（技术发明类）二等奖。 

数字集成电路故障片上检测技术研究与应用：2016年度计量测试学会科技奖二等奖。

32位星载容错控制计算机系统关键技术及应用：2014年度北京市科学技术奖一等奖。  

星载微处理器系统验证-测试-恢复技术及应用：2012年度国家技术发明奖二等奖。  

龙芯CPU研究集体：2003年度中国科学院杰出科技成就奖。