[1] Built-in Fault-Tolerant Computing Paradigm for Resilient Large-Scale Chip Design A Self-Test, Self-Diagnosis, and Self-Repair-Based Approach, Xiaowei Li, Guihai Yan, Cheng Liu, Book, Springer Nature, 2023.

[2] FPGA overlays in FPGAs for Software Programmers, Hayden Kwok-Hay So and Cheng Liu, Springer Nature, pp285–305. 2016.

期刊文章:

[1] An Energy-Efficient In-Memory Accelerator for Graph Construction and Updating. Chen, M.; Liu, C.（通信）; Liang, S.; He, L.; Wang, Y.; Zhang, L.; Li, H.; and Li, X. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 2024.

[2] MRFI: An Open Source Multi-Resolution Fault Injection Framework for Neural Network Processing. Huang, H.; Liu, C.; Liu（通信）, B.; Li, H.; and Li, X. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI). 2024

[3] Statistical Modeling of Soft Error Influence on Neural Networks. Huang, H.; Xue, X.; Liu, C.（通信）; Wang, Y.; Luo, T.; Cheng, L.; Li, H.; and Li, X. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). 2023.

[4] Accelerating Deformable Convolution Networks with Dynamic and Irregular Memory Accesses. Chu, C.; Liu, C.（通信）; Xu, D.; Wang, Y.; Luo, T.; Li, H.; and Li, X. ACM Transactions on Design Automation of Electronic Systems (TODAES), 28(4): 1–23. 2023.

[5] PDG: A Prefetcher for Dynamic Graph Updating. Zhang, X.; Liu, C.（通信）; Ni, J.; Cheng, Y.; Zhang, L.; Li, H.; and Li, X. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),1–14. 2023

[6] Exploring Winograd convolution for cost-effective neural network fault tolerance. Xue, X.; Liu, C.; Liu（通信）, B.; Huang, H.; Wang, Y.; Luo, T.; Zhang, L.; Li, H.; and Li, X. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI). 2023

[7] HyCA: A hybrid computing architecture for fault-tolerant deep learning. Liu, C.; Chu, C.; Xu, D.; Wang, Y.; Wang, Q.; Li, H.; Li, X.; and Cheng, K. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 41(10): 3400–3413. 2022

[8] Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System. Xu, D.; Zhu, Z.; Liu, C.（通信）; Wang, Y.; Zhao, S.; Zhang, L.; Liang, H.; Li, H.; and Cheng, K. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI). 2021

[9] R2F: A remote retraining framework for AIoT processors with computing errors. Xu, D.; He, M.; Liu, C.(通信); Wang, Y.; Cheng, L.; Li, H.; Li, X.; and Cheng, K. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 29(11): 1955–1966. 2021.

[10] Shengwen Liang, Ying Wang, Cheng Liu, Lei He, Huawei Li, Dawen Xu, Xiaowei Li. "EnGN: A High-Throughput and Energy-Efficient Accelerator for Large Graph Neural Networks", IEEE Transactions on Computers (TC), 2020. (Best Paper Award)

会议文章：

[1] DRIM-ANN: An Approximate Nearest Neighbor Search Engine based on Commercial DRAM-PIMs, Mingkai Chen, Tianhua Han, Cheng Liu (通信), Shengwen Liang, Kuai Yu, Lei Dai, Ziming Yuan, Ying Wang, Lei Zhang, Huawei Li, Xiaowei Li, The International Conference for High Performance Computing, Networking, Storage, and Analysis (SC), 2025.

[2] Graphitron: A Domain Specific Language for FPGA-based Graph Processing Accelerator Generation. Xinmiao Zhang, Feng, Zhen, Shengwen Liang, Xinyu Chen, Lei Zhang, and Cheng Liu (通信), The 26th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES). 2025

[3] FrontOrder: Frontier-guided Graph Reordering. Xinmiao Zhang, Cheng Liu (通信), Shengwen Liang, Chengwei Xiong, Yu Zhang, Lei Zhang; Huawei Li, and Xiaowei Li, IEEE International Conference on Data Engineering (ICDE), 2025.

[4] NeuVSA: A Unified and Efficient Accelerator for Neural Vector Search. Yuan, Z.; Dai, L.; Li, W.; Zhang, J.; Wang, Y.; Liu, C.; Li, H.; Li, X.; Guo, J.; Wang, P.; Chen, R.; and Zhang, G. The 31st IEEE International Symposium on High-Performance Computer Architecture (HPCA). 2025

[5] LUT-DLA: Lookup Table as Efficient Extreme Low-Bit Deep Learning Accelerator. Li, G.; Chen, C.; Ye, S.; Wang, Y.; Yang, F.; Cao, T.; Aly, M. M. S.; Liu, C.; and Yang, M. The 31st IEEE International Symposium on High-Performance Computer Architecture (HPCA). 2025.

[6]TaijiGraph: An Out-of-core Graph Processing System Enhanced with Computational Storage. Zhang, X.; Liu, C.(通信); Liang, S.; So, H. K.; Wang, Y.; Zhang, L.; Li, H.; and Li, X. The 39th IEEE International Parallel & Distributed Processing Symposium (IPDPS). 2025.

[7] HLSPilot: LLM-based High-Level Synthesis. Xiong, C.; Liu, C.（通信）; Li, H.; and Li, X. In 2024 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 1–9, 2024

[8]DeepBurning-MixQ: An Open Source Mixed-Precision Neural Network Accelerator Design Framework for FPGAs. Luo, E.; Huang, H.; Liu, C.（通信）; Li, G.; Yang, B.; Wang, Y.; Li, H.; and Li, X. In 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), pages 1–9, 2023. IEEE

[9] Winograd convolution: A perspective from fault tolerance. Xue, X.; Huang, H.; Liu, C.（通信）; Luo, T.; Zhang, L.; and Wang, Y. In Proceedings of the 59th ACM/IEEE Design Automation Conference (DAC), pages 853–858, 2022.

[10] GLIST: Towards In-storage Graph Learning. Li, C.; Wang, Y.; Liu, C.（通信）; Liang, S.; Li, H.; and Li, X. In 2021 USENIX Annual Technical Conference (ATC), pages 225–238, 2021

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华为奥林帕斯先锋奖，2024年

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DAC、FPT、DFTS、ICML、NeurIPS、TC、TPDS、TVLSI等会议和期刊的审稿人