邮箱登录 | 所务办公 | 收藏本站 | English | 中国科学院
 
首页 计算所概况 新闻动态 科研成果 研究队伍 国际交流 技术转移 研究生教育 学术出版物 党群园地 科学传播 信息公开
国际交流
交流动态
学术活动
现在位置:首页 > 国际交流 > 学术活动
Balancing FPGA performance and design productivity of FPGA acceleration 
2018-04-19 | 【 【打印】【关闭】

  时间:2018年4月23日(周一)上午10:00

  地点:计算所421会议室

  报告人:Cheng Liu, National University of Singapore

  摘要:Developing applications that run on FPGAs is without doubt a very different experience from writing programs in software. Not only is the hardware design process fundamentally different from that of software development, software programmers also often find themselves constantly battling with the much lower design productivity in developing hardware designs. FPGA overlay, which is a virtual reconfigurable architecture overlaying on top of the physical FPGA configurable fabrics is generating a lot of excitements because of their potentials to address the design producitivity problem and is gaining traction among researchers recently.

  In this talk, I will present a soft coarse grained reconfigurable array (SCGRA) overlay based loop accelerator generation framework named QuickDough. It targets typical CPU-FPGA architectures and is able to produce hardware accelerators rapidly. Given a user-designated loop for acceleration, QuickDough automatically generates and optimizes the corresponding hardware accelerator and its associated data I/O facilities with the host software.

  报告人简介:Cheng Liu is a research fellow in school of computing at National University of Singapore. He got PhD degree from the University of Hong Kong. Before that, he got B.Eng and Msc from Harbin Institute of Technology. His research interests include FPGA overlay, FPGA acceleration and reconfigurable computing.

 
网站地图 | 联系我们 | 意见反馈 | 所长信箱
 
京ICP备05002829号 京公网安备1101080060号